Search results for "NAND gate"
showing 10 items of 18 documents
Nanomagnetic Self-Organizing Logic Gates
2021
The end of Moore's law for CMOS technology has prompted the search for low-power computing alternatives, resulting in several promising proposals based on magnetic logic[1-8]. One approach aims at tailoring arrays of nanomagnetic islands in which the magnetostatic interactions constrain the equilibrium orientation of the magnetization to embed logical functionalities[9-12]. Despite the realization of several proofs of concepts of such nanomagnetic logic[13-15], it is still unclear what the advantages are compared to the widespread CMOS designs, due to their need for clocking[16, 17] and/or thermal annealing [18,19] for which fast convergence to the ground state is not guaranteed. In fact, i…
Can Atmospheric Neutrons Induce Soft Errors in NAND Floating Gate Memories?
2009
Atmospheric neutrons can interact with the matter inside a microelectronic chip and generate ionizing particles, which in turn can change the state of one or more memory bits [soft error (SE)]. In this letter, we show that SEs are possible in Flash memories, although with extremely low probabilities. While this problem will increase for future technologies, we do not expect SEs to be the reliability limiting factor for further floating gate scaling.
Heavy ion SEE studies on 4-Gbit NAND-Flash memories
2007
Heavy ion SEE studies on three 4-Gbit NAND-flash memory types were performed at the RADEF facility at the University of Jyvaskyla, Finland with particular emphasis on SEFI differentiation. An error classification for complex memory devices is introduced, and respective cross sections are reported.
MBU characterization of NAND-Flash memories under heavy-ion irradiation
2011
The angular dependence of the MBU-Cross-Section of two 8-Gbit-SLC-NAND-Flash and the orientation of the MBU-pattern has been measured.
Improving MLC flash performance and endurance with extended P/E cycles
2015
The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a t…
Comparison of TID response and SEE characterization of single- and multi-level high density NAND flash memories
2009
Heavy ion single-event measurements and total ionizing dose (TID) response for 8Gb commercial NAND flash memories are reported. Radiation results of multilevel flash technology are compared with results from single-level flash technology. The single-level devices are less sensitive to single event upsets (SEUs) than multi-level devices. In general, these commercial high density memories exhibit less TID degradation compared to older generations of flash memories. The charge pump in this study survived up to 600 krads.
Extending SSD lifetime in database applications with page overwrites
2013
Flash-based Solid State Disks (SSDs) have been a great success story over the last years and are widely used in embedded systems, servers, and laptops.One often overlooked ability of NAND flash is that flash pages can be overwritten in certain circumstances. This can be used to decrease wear out and increase performance.In this paper, we analyze the potential of overwrites for the most used data structure in database applications: the B-Tree. We show that with overwrites it is possible to significantly reduce flash wear out and increase overall performance.
Nanocrystal memories for FLASH device applications
2004
Nanocrystals memory cells, in which the conventional polysilicon floating gate is replaced by an array of silicon nanocrystals, have been fabricated and characterized. Single cells and cell arrays of 1 Mb and 10 k have been realized by using a conventional 0.15 μm FLASH technology. Si nanocrystals are deposited on top of tunnel oxide by chemical vapor deposition. Properties of the memory cell have been investigated both for NAND and NOR applications in terms of program/erase window and programming times. Suitable program/erase threshold voltage window can be achieved with fast voltage pulses by adequate choice of tunnel and control dielectric. The feasibility of dual bit storage is also pro…
How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
2004
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
Effects of high-energy electrons in advanced NAND flash memories
2016
We study the effects of high-energy electrons on advanced NAND Flash memories with multi-level and single-level cell architecture. We analyze the error rate in floating gate cells as a function of electron energy, evaluate the impact of total ionizing dose, and discuss the physical origin of the observed behavior.